1. Field of Invention
Exemplary embodiments of the present invention relate to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit for performing a reset operation.
2. Description of Related Art
Generally, in a memory device, when an input of data from the outside is completed, an input of a command is permitted after a fixed time, for example, 2 cycles of a clock signal, is elapsed. In a flash memory device, after data is input, the input of the command is prohibited while the data is transferred to a read/write circuit, for example, a page buffer. Hereinafter, such fixed time (or period) is referred to as a command-masking period. Thus, after completing the data input, a reset operation may not be performed for the command-masking period, and the reset operation may be permitted after the command-masking period elapses.